The demand for more powerful computers and communication products has resulted in faster processors and busses that often have higher die temperatures and consume increasing amounts of power. Consequently, design engineers struggle with reducing power consumption and die temperature.
For example, serial busses that utilize serial links, such as, PCI-Express and other link based interconnection systems, utilize an interface that is always transmitting and receiving data. Therefore, one disadvantage of high speed serial links is increased power consumption. Specifically, the physical layer transmitter and receiver can consume a constant DC current, regardless whether the interface is actually transmitting or receiving data.
Various attempts for power management schemes for addressing the increased power consumption for serial links and serial busses have been proposed and implemented. However, they require time to put the serial link to sleep and time to wake the link up again. Consequently, the latency required for transitioning between power management states adversely impacts performance in a microprocessor environment.